Generally, integrated circuits include a complex network of conductive interconnects fabricated on a semiconductor substrate in which semiconductor devices have been formed. Efficient routing of these interconnects requires formation of multilevel or multilayered schemes, such as, for example, single or dual damascene wiring structures.
Within an interconnect structure, conductive vias run perpendicular to the semiconductor substrate and conductive lines run parallel to the semiconductor substrate. According to conventional damascene processing, lines and vias are created within a dielectric layer. A dielectric layer is patterned to create grooves which become lines and holes which become vias. Metal is deposited on the patterned surface such as by electroplating to fill the grooves and holes. Excess is removed, such as by CMP, thereby forming lines along the top of a given dielectric layer, and forming vias which extend below the lines in order to connect to an underlying layer.
There is a continuing need to increase density by, for example, shrinking the size of the conductive interconnects. As feature size continues to decrease, the limitations of copper electroplating to fill features formed in dielectric are increasingly apparent. Copper typically requires a barrier layer to prevent it from migrating and degrading the insulating capacity of surrounding dielectric material. Shrinking the feature size generally requires higher aspect ratios, which are increasingly difficult to fill, and furthermore, the barrier layer cannot scale and hence constitutes a greater fraction of any particular feature.
Feature density can also be increased by reducing the spacing between features, but closely spaced features can suffer from increased capacitive coupling. Low k dielectrics, having k value of 3.0 or less, can be employed but are susceptible to TDDB (time dependent dielectric breakdown) and are challenging to etch, leading to issues such as poor profile control, voids, and collapse. Air gaps have much lower k value approaching 1.0, but pose various fabrication challenges. Several prior art references utilize a sacrificial material, form interconnect structure by dielectric damascene, then remove the sacrificial material to open air gaps below or between such interconnect structure. See, e.g., U.S. Pat. No. 7,595,555, U.S. Pat. No. 7,329,602, U.S. Pat. Nos. 6,861,332, and 6,908,829. These techniques require lithography and other processes in order to selectively remove the sacrificial material.
An alternative to forming the interconnect structure by copper damascene is subtractive metal etch (“SME”). U.S. Pat. No. 5,668,398 proposed using a sacrificial layer to fill between SME structures, utilizing lithography steps to remove the sacrificial material, like in the above cases. U.S. Pat. No. 6,399,476 (“Kim et al.”) discloses forming air gaps between lines formed by SME by a “multilayer passivation process” that avoids use of a sacrificial material. Referring to FIG. 1A, which is FIG. 4 of Kim et al., an intermetal dielectric layer 104 is disposed over a first metal interconnection 102. Second spaced metal interconnections 106 are formed by depositing a second metal layer over layer 104 and etching according to a patterned photoresist (col. 4, lines 26-39). The photoresist is removed and features 106 are coated with a multilayer dielectric. The first layer 108 is “deposited thickly at the top portion, specifically top sides of the second metal interconnections, while being deposited very thin at the bottom sides” thereby modifying the space between adjacent conductors to have “a relatively narrow opening size as compared to the size of its bottom.” (col. 3, lines 50-58 and col. 4, lines 47-66). A second layer 112 of the multilayer dielectric is deposited “to a thickness condition that forms air gaps 114” (col. 5, lines 4-7). A “third conventional passivation layer 116” is then deposited and planarized. According to Kim et al., “a conventional photography process is conducted and a metal contact pad (not shown) is formed in the third passivation layer 116 to the selected second metal interconnections. Subsequently, a process for forming other metal interconnections is further carried out.” ['476 col. 5 lines 25-35].
However, a problem with the technique of Kim et al. can arise upon attempting to connect a subsequent layer of metal interconnections. Referring now to FIG. 1B, to do so requires forming a patterned mask 120 and forming openings 121 and 122 through the dielectric to expose an underlying metal wire. As feature sizes shrink, alignment of the mask with underlying wires is increasingly difficult, therefore landing (i.e., forming the vertical interconnect exactly on the underlying wire) is also. Etching through a misaligned opening 122 can pierce layer 112 and form opening 131 into the adjacent air gap 114. Even with better alignment, over etching or just an unfortunately located flaw in layer 112, can puncture the encapsulated air gap. During subsequent deposition of a next metal layer, the open air gap will fill with metal, potentially shorting the adjacent features.